603 Hardware Specifications, REV 2 9
Preliminary—Subject to Change without Notice
Figure 2. Input Timing Diagram
Figure 3. Mode Select Input Timing Diagram
1.3.2.3 Output AC Specifications
Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications
are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
Table 7. Output AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C
L
= 50 pF, 0
≤
T
J
≤
105
°
C
Num Characteristic
25 33.33 40 50 66.67
Unit Notes
Min Max Min Max Min Max Min Max Min Max
12 SYSCLK to output
driven (output enable
time)
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
13a SYSCLK to output
valid (5.5 V to
0.8 V— TS, ABB,
AR
TRY, DBB)
— 14.0 — 13.0 — 12.0 — 11.0 — 10.0 ns 4
13b SYSCLK to output
valid (TS, ABB,
ARTRY, DBB)
— 13.0 — 12.0 — 11.0 — 10.0 — 9.0 ns 6
VMSYSCLK
VM = Midpoint Voltage (1.4V)
11a
ALL INPUTS
10b
10a
11b
MODE PINS
HRESET
10c
11c
VM
VM = Midpoint Voltage (1.4 V)
