A SERVICE OF

logo

Open as PDF
next previous
June 3, 2004 Document No. 38-12009 Rev. *E 23
CY8C22x13 Final Data Sheet 3. Electrical Specifications
Figure 3-3. PLL Lock for Low Gain Setting Timing Diagram
Figure 3-4. External Crystal Oscillator Startup Timing Diagram
Figure 3-5. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 3-6. 32 kHz Period Jitter (ECO) Timing Diagram
24 MHz
F
PLL
PLL
E
nable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
S
elect
T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
[+] Feedback