2.13TransferNodePriority
2.14ResetConsiderations
2.14.1SoftwareResetConsiderations
PeripheralArchitecture
Latencytosystem’sinternalandexternalRAMcanbecontrolledthroughtheuseofthetransfernode
priorityallocationregisteravailableatthedevicelevel.LatencytodescriptorRAMislowbecauseRAMis
localtotheEMAC,asitispartoftheEMACcontrolmodule.
TheDM643xdevicecontainsachip-levelregister,masterpriorityregister(MSTPRI),thatisusedtoset
thepriorityofthetransfernodeusedinissuingmemorytransferrequeststosystemmemory.
AlthoughtheEMAChasinternalFIFOstohelpalleviatememorytransferarbitrationproblems,theaverage
transferrateofdatareadandwrittenbytheEMACtointernalorexternalprocessormemorymustbeat
leastthatoftheEthernetwirerate.Inaddition,theinternalFIFOsystemcannotwithstandasingle
memorylatencyeventgreaterthanthetimeittakestofilloremptyaTXCELLTHRESHnumberofinternal
64byteFIFOcells.
For100Mbpsoperation,theserestrictionstranslateintothefollowingrules:
•Theshort-termaverage,each64-bytememoryread/writerequestfromtheEMACmustbeservicedin
nomorethan5.12µs.
•Anysinglelatencyeventinrequestservicingcanbenolongerthan(5.12×TXCELLTHRESH)µs.
Bits[0-2]ofthesecondchip-levelmasterpriorityregister(MSTPRI1)areusedtosetthetransfernode
prioritywithintheSwitchedCentralResource(SCR5)fortheEMACmasterperipheral.
Avalueof000bhasthehighestpriority,while111bhasthelowestpriority.Thedefaultpriorityassignedto
theEMACis100b.Itisimportanttohaveabalancebetweenallperipherals.Inmostcases,thedefault
prioritieswillnotneedadjustment.Formoreinformationonthemasterperipheralspriorities,seethe
device-specificdatamanual.
PeripheralclockandresetcontrolisdonethroughthePowerandSleepController(PSC)moduleincluded
withthedevice.FormoreonhowtheEMAC,MDIO,andEMACcontrolmodulearedisabledorplacedin
resetatruntimefromtheregisterslocatedinthePSCmodule,seeSection2.17.
WiththeEMACstillinreset(PSCinthedefaultstate):
1.ProgramthePINMUX1registertoHOSTBK=3hor4h(MII).
2.ProgramtheVDD3P3V_PWDNregistertopoweruptheIOpinsforMIIpins(seethedevice-specific
datamanual).
3.ProgramthePSCtoenaletheEMAC.ForinformationonhowtoenabletheEMACperipheralfromthe
PSC,seetheTMS320DM643xDMPDSPSubsystemReferenceGuide(SPRU978).
Withintheperipheralitself,theEMACcomponentoftheEthernetMACperipheralcanbeplacedinareset
statebywritingtothesoftresetregister(SOFTRESET).Writinga1totheSOFTRESETbit,causesthe
EMAClogictoberesetandtheregistervaluestobesettotheirdefaultvalues.Softwareresetoccurs
whenthereceiveandtransmitDMAcontrollersareinanidlestatetoavoidlockinguptheconfiguration
bus;itistheresponsibilityofthesoftwaretoverifythattherearenopendingframestobetransferred.
Afterwritinga1totheSOFTRESETbit,itmaybepolledtodetermineiftheresethasoccurred.Ifa1is
read,theresethasnotyetoccurred;ifa0isread,thenaresethasoccurred.
Afterasoftwareresetoperation,alltheEMACregistersneedtobereinitializedforproperdata
transmission,includingtheFULLDUPLEXbitsettingintheMACcontrolregister(MACCONTROL).
UnliketheEMACmodule,theMDIOandEMACcontrolmodulescannotbeplacedinresetfromaregister
insidetheirmemorymap.
SPRU941A–April2007EthernetMediaAccessController(EMAC)/45
ManagementDataInput/Output(MDIO)
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