5.31EmulationControlRegister(EMCONTROL)
5.32FIFOControlRegister(FIFOCONTROL)
EthernetMediaAccessController(EMAC)Registers
Theemulationcontrolregister(EMCONTROL)isshowninFigure71anddescribedinTable70.
Figure71.EmulationControlRegister(EMCONTROL)
3116
Reserved
R-0
15210
ReservedSOFTFREE
R-0R/W-0R/W-0
LEGEND:R=Readonly;R/W=Read/Write;-n=valueafterreset
Table70.EmulationControlRegister(EMCONTROL)FieldDescriptions
BitFieldValueDescription
31-2Reserved0Reserved
1SOFT0-1Emulationsoftbit
0FREE0-1Emulationfreebit
TheFIFOcontrolregister(FIFOCONTROL)isshowninFigure72anddescribedinTable71.
Figure72.FIFOControlRegister(FIFOCONTROL)
31232216
ReservedRXFIFOFLOWTHRESH
R-0R/W-2h
15540
ReservedTXCELLTHRESH
R-0R/W-18h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table71.FIFOControlRegister(FIFOCONTROL)FieldDescriptions
BitFieldValueDescription
31-23Reserved0Reserved
22-16RXFIFOFLOWTHRESH0-3FhReceiveFIFOflowcontrolthreshold.OccupancyofthereceiveFIFOwhenreceive
FIFOflowcontrolistriggered(ifenabled).Thedefaultvalueis2h,whichmeansthat
receiveFIFOflowcontrolistriggeredwhentheoccupancyoftheFIFOreaches2cells.
15-5Reserved0Reserved
4-0TXCELLTHRESH0-1FhTransmitFIFOcellthreshold.Indicatesthenumberof64-bytepacketcellsrequiredto
beinthetransmitFIFObeforethepackettransferisinitiated.Packetswithfewercells
areinitiatedwhenthecompletepacketiscontainedintheFIFO.Thisvaluemustbe
greaterthanorequalto2andlessthanorequalto24(2≥TXCELLTHRESH≤24).
114EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)SPRUEQ6–December2007
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