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SYS Module
Figure 5: PLL mode hardware configuration
PLLVDD (L15)
PLLVSS (L12)
RESET* (A10)
PLLTST (N15)
BISTEN (M15)
SCANEN (L13)
ND
FS
IS
BCLK
FXTAL
XTALA1 (K14)
XTALA2 (K12)
1.5V
3.3V
10 K
A0
A1
A2
A3
A4
A5
A6
A7
A8
The NS7520 address
bus has internal
pullups.
2.7K pulldown
resistors can be
connected to the
address lines to
configure the PLL
settings at bootup.
Tie high to use the
JTAG debugger.
Connect to ground to
use boundary scan
testing.
MAX811 or other
power-on reset
circuit