Epson Research and Development Page 91
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. Ts = pixel clock period
Table 6-27: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Symbol Parameter Min Typ Max Units
t1
Vertical total period 203 264 Lines
t2
Vertical display start position 40 Lines
t3
Vertical display period 160 Lines
t4
Vertical sync pulse width 2 Lines
t5
FPFRAME falling edge to GPIO1 alternate timing start 5 Lines
t6
GPIO1 alternate timing period 4 Lines
t7
FPFRAME falling edge to GPIO0 alternate timing start 40 Lines
t8 GPIO0 alternate timing period 162 Lines
t9 GPIO1 first pulse rising edge to FPLINE rising edge 4 Ts (note 1)
t10 GPIO1 first pulse width 48 Ts
t11 GPIO1 first pulse falling edge to second pulse rising edge 40 Ts
t12 GPIO1 second pulse width 48 Ts
t13 GPIO0 falling edge to FPLINE rising edge 4 Ts
t14 GPIO0 low pulse width 24 Ts
