Instruction List (2)
S1C6200 Core CPU
Opcode
PSET
JP
JPBA
CALL
CALZ
RET
RETS
RETD
NOP5
NOP7
HALT
SLP
INC
LD
ADC
Clasiffication
Branch
instructions
System
control
instructions
Index
operation
instructions
Operand
p
s
C, s
NC, s
Z, s
NZ, s
s
s
l
X
Y
X, x
Y, y
XP, r
XH, r
XL, r
YP, r
YH, r
YL, r
r, XP
r, XH
r, XL
r, YP
r, YH
r, YL
XH, i
XL, i
YH, i
YL, i
Function
NPB←p[4], NPP←p[3:0]
PCB←NBP, PCP←NPP, PCS←s
PCB←NBP, PCP←NPP, PCS←s, if C=1
PCB←NBP, PCP←NPP, PCS←s, if C=0
PCB←NBP, PCP←NPP, PCS←s, if Z=1
PCB←NBP, PCP←NPP, PCS←s, if Z=0
PCB←NBP, PCP←NPP, PCSH←B, PCSL←A
M(SP-1)←PCP, M(SP-2)←PCSH, M(SP-3)
←PCSL+1, SP←SP-3, PCP←NPP, PCS←s
M(SP-1)←PCP, M(SP-2)←PCSH, M(SP-3)
←PCSL+1, SP←SP-3, PCP←0, PCS←s
PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2), SP←SP+3
PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2), SP←SP+3, PC←PC+1
PCSL←M(SP), PCSH←M(SP+1), PCP←M(SP+2), SP←SP+3, M(X)←l[3:0], M(X+1)←l[7:4], X←X+2
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop CPU)
Sleep (stop CPU and oscillation)
X←X+1
Y←Y+1
XH←x[7:4], XL←x[3:0]
YH←y[7:4], YL←y[3:0]
XP←r
XH←r
XL←r
YP←r
YH←r
YL←r
r←XP
r←XH
r←XL
r←YP
r←YH
r←YL
XH←XH+i+C
XL←XL+i+C
YH←YH+i+C
YL←YL+i+C
Clk
5
5
5
5
5
5
5
7
7
7
12
12
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
1
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↔
↔
↔
↔
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↔
↔
↔
↔
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
0
Code
MSB LSB
Mnemonic
Flags
Remarks
p
s
s
s
s
s
s
s
l
x
y
r
r
r
r
r
r
r
r
r
r
r
r
i
i
i
i
