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2
SECTION 2 - SYSTEM DESCRIPTION
The following sections describe the major system features of the IRV-686 All-In-One Single Board
Computer.
PROCESSOR
The IRV-686 Pentium SBC supports 100MHz to 233MHz Pentium/MMX, and the AMD K6-2
processor up to 333MHz. It also supports the Cyrix 6x86-PR266. The Pentium microprocessor
includes an on-chip 16K-byte unified instruction cache, an 16K-byte data cache, an internal high
performance math co-processor, and an enhanced 64-bit data bus. The on-board jumper selectable
clock generator and ZIF CPU socket makes upgrading to a higher performance CPU easy. Some of
the distinctive features of the processors include:
64-bit External Data Bus
32-bit Internal Architecture
256M-byte Directly Addressable Memory Space
Internal 14 Word by 32-bit Register Set
Separate 8K-byte Data and Cache Memories
On-chip Pipelined Floating Point Processor
Integrated Memory Manager
SYSTEM MEMORY (DRAM)
The IRV-686 Pentium SBC can support up to 256M-bytes of synchronous dynamic random access
memory (SDRAM) organized as two banks of 16Mx72 including eight parity bits. The memory is
configured using two dual in-line memory module sockets, which will accept 168-pin dual in-line
memory modules (DIMMs) organized as 16MB, 32MB, 64MB, or 128MB with a maximum access
time of 15ns.
CACHE MEMORY
The IRV-686 SBC includes 512K-bytes of pipelined burst mode cache memory for high speed access
to blocks of data most recently read from main memory, including buffered data from the disk and
video memory. The cache memory will significantly increase system performance over that of a
conventional non-cached system.
DMA CONTROLLER
The IRV-686 SBC memory refresh and DMA functions are included in the System Controller chip
which includes the equivalence of two 82C37 DMA controllers. The two DMA controllers are
cascaded to provide four DMA channels for transfers to 8-bit peripherals (DMA1) and three channels
for transfers to 16-bit peripherals (DMA2). DMA2 Channel 0 provides the cascade interconnection
for the two DMA devices thereby maintaining IBM PC/AT compatibility. The DMA channel
assignments are listed below: