3
DMA Channel 0: Not Used (8-bit)
DMA Channel 1: Alternate for Multi-mode Parallel Port (8-bit)
DMA Channel 2: Floppy Disk (8-bit)
DMA Channel 3: Multi-mode Parallel Port (8-bit)
DMA Channel 5: Not Used (16-bit)
DMA Channel 6: Not Used (16-bit)
DMA Channel 7: Not Used (16-bit)
The DMA request (DRQx) and acknowledge (DACKx/) lines are available on the P1 98-pin edge
connector.
INTERRUPT CONTROLLER
The IRV-686 SBC has the equivalence of two 82C59A interrupt controllers included in the System
Controller chip. The controllers accept requests from peripherals, resolve priorities on pending
interrupts and interrupts in service, interrupt the CPU, and provide the vector address of the
interrupt service routine. The two interrupt controllers are cascaded in a fashion compatible with the
IBM PC/AT. The interrupt priority and assignments are shown below in descending order of
priority:
Highest IOCHCK/ Parity Check (Non-maskable)
IRQ0 System Timer (Not Available)
IRQ1 Keyboard (Not Available)
IRQ8 Real Time Clock (Not Available)
IRQ9 SVGA Controller
IRQ10 Not Used
IRQ11 Not Used
IRQ12 Not Used
IRQ13 Co-processor (Not Available)
IRQ14 EIDE Disk Controller
IRQ15 Not Used
IRQ3 Serial Port 2
IRQ4 Serial Port 1
IRQ5 Alternate for Parallel Port
IRQ6 Floppy Disk Controller
Lowest IRQ7 Parallel Port
The interrupt request lines IRQx and IOCHCK/ are available on the 98-pin edge connector except as
noted above.
