4.12 SECTION FOUR - COMPONENT DESCRIPTION AND SPECIFICATION
The Built In Test (BIT) output of the R/D converter is monitored. Logic 0 for BIT condition
indicates ±100 LSBs of error. Causes of BIT error are loss of signal inputs or loss of
resolver reference. When this occurs, the Encoder Simulator outputs will go to a known
state.
Figure 4-7 is a block diagram of the Encoder Simulation option card.
4.4.1.1. A and B Outputs
The A and B outputs are in quadrature, i.e. B will lead A by 90° when the motor is rotating
clockwise (CW) as viewed looking at the motor front mounting plate and A will lead B by
90° when the motor is rotating counterclockwise (CCW). The phase relationship of A and
B can be used to determine motor direction.
Since the Encoder Simulator outputs are in true quadrature, the ripple associated with the
duty cycle variation of a normal encoder is avoided when using X2 or X4 counting
schemes.
The resolution of the Encoder Simulator, in pulses per revolution (ppr), is selectable from
128 ppr to 16384 ppr. The factory default resolution is 256 ppr. The allowable motor
operating speed range is reduced at higher Encoder Simulator resolutions as indicated in
Table 4-3.
R/D Resolution
(Bits)
Line Count
(Pulse Per Rev)
Motor Speed Range
(RPM)
16 16384 0-1400
16 8192 0-1400
14 4096 0-6000
14 2048 0-6000
12 1024 0-15000
12 512 0-15000
10 256 0-15000
10 128 0-15000
TABLE 4-4. ENCODER SIMULATOR CONFIGURATION OPTIONS
