HyperTransport
TM
Technology
The Next-Generation AMD Opteron processor continues to use HyperTransport Technology links to
provide a scalable bandwidth interconnect among processors, I/O subsystems, and other chip sets.
HyperTransport Technology:
• Helps increase overall system performance by removing I/O bottlenecks typically found in Front Side
Bus (FSB) architectures and efficiently integrating with legacy buses, increasing bandwidth and speed,
and reducing latency of processors.
• Provides up to 8 GB/sec. bandwidth per link at 16x16 bits, 1 GHz operation, providing sufficient
bandwidth for supporting new interconnects, such as PCI-Express.
Intel's Front-side Bus (FSB) Architecture AMD Direct Connect Architecture
Figure 2: Intel versus AMD processor Architecture
Intel's Front Side Bus (FSB) architecture requires a separate memory controller. I/O bottlenecks and
reduced efficiencies are seen as data from CPU to CPU, CPU to I/O and CPU to memory all funnel
through a central Front-Side Bus.
Just the Facts, August 2007 Sun Confidential: Internal and Sun Channel Partners Use Only 16
I/O Hub
USB
PCI
PCIc™
Bridge
PCIc™
Bridge
SRQ
Crossbar
HT
Mem.Ctrlr
SRQ
Crossbar
HT
Mem.Ctrlr
8 GB/S
8 GB/S 8 GB/S
8 GB/S
PCI-E
Bridge
I/O Hub
CPU CPU
Core Core Core Core
I/O Hub
PCI-E
Bridge
PCI-E
Bridge
PCIc™
Bridge
Memory
Controller
Hub
