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CLRC
Clear Control Bit
7-62
Syntax CLRC
control bit
Operands control bit: Select one of the following control bits:
C Carry bit of status register ST1
CNF RAM configuration control bit of status register ST1
INTM Interrupt mode bit of status register ST0
OVM Overflow mode bit of status register ST0
SXM Sign-extension mode bit of status register ST1
TC Test/control flag bit of status register ST1
XF XF pin status bit of status register ST1
CLRC C
0123456789101112131415
0111001001111101
CLRC CNF
0123456789101112131415
0010001001111101
CLRC INTM
0123456789101112131415
0000001001111101
CLRC OVM
0123456789101112131415
0100001001111101
CLRC SXM
0123456789101112131415
0110001001111101
CLRC TC
0123456789101112131415
0101001001111101
CLRC XF
0123456789101112131415
0011001001111101
Execution Increment PC, then ...
0 control bit
Status Bits None
Description The specified control bit is cleared to 0. Note that the LST instruction can also
be used to load ST0 and ST1. See subsection 3.5,
Status Registers ST0 and
ST1
on page 3-15, for more information on each of these control bits.
Opcode