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ATM Cell Traffic Flow in the 9A656-04
The 9A656-04 SmartSwitch utilizes several innovative features that result in a
completely redundant, fault-tolerant design. The three most important hardware
facets of the 9A656-04 SmartSwitchÕs features are the Cell Transfer Matrix,
Cabletron Systems ASICs, and the i960 HD RISC Processor.
Cell Transfer Matrix (CTM)
The Cell Transfer Matrix provides a Time Division Multiplexed (TDM) based
mesh of full duplex, high-speed (1.6 Gbps) interconnections that carry standard
ATM cell trafÞc. These interconnections are in fact a series of point-to-point links
between an individual module and every other module in the chassis. Each
9A656-04 has 14 physical CTM interfaces; one connection to every other 9A656-04
along with a local loopback interface. A SmartSwitch 9500 chassis with 14 9A656-
04 modules installed would have 182 point-to-point links between all the
interface modules. This enables the SmartSwitch 9500 to provide an aggregate
switching capacity of 63 Gbps if 14 modules are connected to the CTM backplane.
Cabletron Systems ASICs
The 9A656-04 SmartSwitch utilizes Þve separate Cabletron Systems designed
ASICs to perform switching functions. Refer to Figure 3-1 to see how these Þve
ASICs work together to provide proper trafÞc ßow. The deÞnitions for these
ASICs are as follows:
Queue ASIC
The 9A656-04 has four Queue ASICs installed on the motherboard. These ASICs
support 16 priority queues each. The Queue ASICs support all classes of ATM
service including Constant Bit Rate (CBR), Variable Bit Rate (VBR), Available Bit
Rate (ABR) and UnspeciÞed Bit Rate (UBR). The Queue ASICs also manage all cell
transfers to the Utopia ASICs, using a weighted round-robin algorithm.
TDM (Time Division Multiplexer) ASIC
The TDM ASIC is the central switching engine of the 9A656-04. The TDM ASIC
maintains the connections table, gathers statistics, and provides Usage Parameter
Control (UPC) policing. The TDM ASIC supports up to 128k virtual connections.
SARI (Segmentation and Reassembly Interface) ASIC
The SARI ASIC is the interface that controls the data ßow between the TDM Bus
and the i960 Host Processor. The SARI ASIC has a 768-cell queue and provides the
trafÞc management features of the 9A656-04.
The interconnections exist only between modules that are directly attached to the
CTM.
NOTE