Dell T610 Manual

A SERVICE OF

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Dell™ PowerEdge™ T610 Technical Guidebook

27

SECTION 7. MEMORY

A. Overview / Description

The PowerEdge T610 utilizes DDR3 memory providing a high performance, high‑speed memory

interface capable of low latency response and high throughput. The PowerEdge T610 supports

Registered ECC DDR3 DIMMs (RDIMM) or Unbuered ECC DDR3 DIMMs (UDIMM).

Key features of the PowerEdge T610 memory system include:

 •Registered(RDIMM)andUnbuered(UDIMM)DDR3technology

 •Eachchannelcarries64dataandeightECCbits

 •Supportforupto96GBofRDIMMmemory(with8GBRDIMMs)

 •Supportforupto24GBofUDIMMmemory(with2GBUDIMMs)

 •Supportfor1066/1333MHzsingleanddualrankDIMMs

 •Supportfor1066MHzquadrankDIMMs

 •SingleDIMMcongurationwithDIMMatsocketDIMMA1

 •SupportODT(OnDieTermination)

 •Clockgating(CKE)toconservepowerwhenDIMMsarenotaccessed

 •DIMMswillenteralow-powerself-refreshmode

 •I2CaccesstoSPDEEPROMandthermalsensors

 •SingleBitErrorCorrection

 •SDDC(SingleDeviceDataCorrection–x4orx8devices)

 •MultiBitErrorDetection

 •SupportforClosedLoopThermalManagementonRDIMMsandUDIMMs

 •SupportforAdvancedECCmode

 •SupportforMemoryOptimizedmode

 •SupportforMemoryMirroring

 •NosupportforMemorySparing

B. DIMMs Supported

The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per

channel for single/dual rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB,

4GB, or 8GB RDIMMs; only 1GB or 2GB UDIMMs are supported. The memory mode is dependent on how

the memory is populated in the system:

 •ThreechannelsperCPUpopulatedidentically

  •Typically,thesystemwillbesettoruninMemoryOptimized(IndependentChannel)

mode in this conﬁguration. This mode oers the most DIMM population ﬂexibility and

system memory capacity, but oers the least number of RAS (reliability, availability,

service) features.

  •Allthreechannelsmustbepopulatedidentically.

 •ThersttwochannelsperCPUpopulatedidenticallywiththethirdchannelunused

  •Typically,twochannelsoperateinAdvancedECC(Lockstep)modewitheachotherby

having the cache line split across both channels. This mode provides improved RAS

features (SDDC support for x8‑based memory).

  •ForMemoryMirroring,twochannelsoperateasmirrorsofeachother—writesgoto

both channels and reads alternate between the two channels.

 •OnechannelperCPUpopulated

  •ThisisasimpleMemoryOptimizedmode.Nomirroringorsparingissupported.

The PowerEdge T610 memory interface supports memory demand and patrol scrubbing, single‑bit

correction and multi‑bit error detection. Correction of a x4 or x8 device failure is possible through the