S1C63000 CORE CPU MANUAL EPSON 139
CHAPTER 4: INSTRUCTION SET
TST [addr6],imm2
XOR %r,%r’ Exclusive OR r’ reg. and r reg. 1 cycle
Function: r ← r ∀ r’
Performs an exclusive OR operation of the content of the r’ register (A or B) and the content of
the r register (A or B), and stores the result in the r register.
Code:
Mnemonic MSB LSB
XOR %A,%A 110111111000X1BF0H, (1BF1H)
XOR %A,%B 110111111001X1BF2H, (1BF3H)
XOR %B,%A 110111111010X1BF4H, (1BF5H)
XOR %B,%B 110111111011X1BF6H, (1BF7H)
Flags: EICZ
↓ ––↕ (r ≠ r’)
↓ ––↑ (r = r’)
Mode: Src: Register direct
Dst: Register direct
Extended addressing: Invalid
Test bit imm2 in location [addr6] 1 cycle
Function: [addr6] ∨ (2
imm2
)
(addr6 = 0000H–003FH or FFC0H–FFFFH)
Tests the bit specified with the imm2 in the data memory specified with the addr6, and sets/
resets the Z flag. It does not change the content of the data memory.
Code:
Mnemonic MSB LSB
TST [00addr6],imm2
10010i1i0a5a4a3a2a1a01200H–12FFH
TST [FFaddr6],imm2
10011i1i0a5a4a3a2a1a01300H–13FFH
Flags: EICZ
↓ ––↕
Mode: Src: Immediate data
Dst: 6-bit absolute
Extended addressing: Invalid
