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S1C63000 CORE CPU MANUAL EPSON 45
CHAPTER 4: INSTRUCTION SET
XOR %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
XOR %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
XOR %F,imm4
XOR [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
XOR [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
BIT %A,%A
%A,%B
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
BIT %B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
BIT [%X],%A
[%X],%B
[%X],imm4
[%X]+,%A
[%X]+,%B
[%X]+,imm4
BIT [%Y],%A
[%Y],%B
[%Y],imm4
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
CLR [00addr6],imm2
[FFaddr6],imm2
SET [00addr6],imm2
[FFaddr6],imm2
TST [00addr6],imm2
[FFaddr6],imm2
110111111000X
110111111001X
110111100i3i2i1i0
1101111100000
1101111100001
1101111100010
1101111100011
110111111010X
110111111011X
110111101i3i2i1i0
1101111100100
1101111100101
1101111100110
1101111100111
100001010i3i2i1i0
1101111101000
1101111101100
110111000i3i2i1i0
1101111101001
1101111101101
110111001i3i2i1i0
1101111101010
1101111101110
110111010i3i2i1i0
1101111101011
1101111101111
110111011i3i2i1i0
110101111000X
110101111001X
110101100i3i2i1i0
1101011100000
1101011100001
1101011100010
1101011100011
110101111010X
110101111011X
110101101i3i2i1i0
1101011100100
1101011100101
1101011100110
1101011100111
1101011101000
1101011101100
110101000i3i2i1i0
1101011101001
1101011101101
110101001i3i2i1i0
1101011101010
1101011101110
110101010i3i2i1i0
1101011101011
1101011101111
110101011i3i2i1i0
10100i1i0
a5a4a3a2a1a0
10101i1i0
a5a4a3a2a1a0
10110i1i0
a5a4a3a2a1a0
10111i1i0
a5a4a3a2a1a0
10010i1i0
a5a4a3a2a1a0
10011i1i0
a5a4a3a2a1a0
1 ↓ ––↑×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ ––↑×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ●
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ●
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ●
1 ↓ –– ●
1 ↓ –– ●
1 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
2 ↓ –– ×
1 ↓ –– ×
1 ↓ –– ×
A ← A∀A
A ← A∀B
A ← A∀imm4
A ← A∀[X]
A ← A∀[X], X ← X+1
A ← A∀[Y]
A ← A∀[Y], Y ← Y+1
B ← B∀A
B ← B∀B
B ← B∀imm4
B ← B∀[X]
B ← B∀[X], X ← X+1
B ← B∀[Y]
B ← B∀[Y], Y ← Y+1
F ← F∀imm4
[X] ← [X]∀A
[X] ← [X]∀B
[X] ← [X]∀imm4
[X] ← [X]∀A, X ← X+1
[X] ← [X]∀B, X ← X+1
[X] ← [X]∀imm4, X ← X+1
[Y] ← [Y]∀A
[Y] ← [Y]∀B
[Y] ← [Y]∀imm4
[Y] ← [Y]∀A, Y ← Y+1
[Y] ← [Y]∀B, Y ← Y+1
[Y] ← [Y]∀imm4, Y ← Y+1
A
∧
A
A
∧
B
A
∧
imm4
A
∧
[X]
A
∧
[X], X ← X+1
A
∧
[Y]
A
∧
[Y], Y ← Y+1
B
∧
A
B
∧
B
B
∧
imm4
B
∧
[X]
B
∧
[X], X ← X+1
B
∧
[Y]
B
∧
[Y], Y ← Y+1
[X]
∧
A
[X]
∧
B
[X]
∧
imm4
[X]
∧
A, X ← X+1
[X]
∧
B, X ← X+1
[X]
∧
imm4, X ← X+1
[Y]
∧
A
[Y]
∧
B
[Y]
∧
imm4
[Y]
∧
A, Y ← Y+1
[Y]
∧
B, Y ← Y+1
[Y]
∧
imm4, Y ← Y+1
[00addr6] ← [00addr6]
∧
not (2
imm2
)
[FFaddr6] ← [FFaddr6]
∧
not (2
imm2
)
[00addr6] ← [00addr6]
∧
(2
imm2
)
[FFaddr6] ← [FFaddr6]
∧
(2
imm2
)
[00addr6]
∧
(2
imm2
)
[FFaddr6]
∧
(2
imm2
)
Mnemonic
Machine code
Operation Cycle Page
Flag EXT.
mode
12
EICZ
11109876543210
ALU logic operation (2/2)
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
↔
↔
↔
↔
↔↔↔↔↔↔
139
139
140
141
141
141
141
139
139
140
141
141
141
141
140
142
142
143
142
142
143
142
142
143
142
142
143
78
78
78
79
79
79
79
78
78
78
79
79
79
79
80
80
81
80
80
81
80
80
81
80
80
81
83
83
131
131
139
139