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2.0 Functional Description
2.4 Channel Unit Interface
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
2.4 Channel Unit Interface
The quaternary signals of the channel unit interface have four modes which are
programmable through bits 0 and 1 of the Channel Unit Interface Modes Register
[cu_interface_modes; 0x06]. They are: serial sign-bit first, serial magnitude-bit
first, parallel master, and parallel slave.
In serial mode, a Bit Rate Clock (BCLK) is output at twice the symbol rate.
The sign and magnitude bits of the receive data are output through RDAT on the
rising edge of BCLK. The sign and magnitude bits of the transmit data are sam-
pled on the falling edge of BCLK at the TDAT input. The sign bit is transferred
first, followed by the magnitude bit of a given symbol in sign-bit first mode, while
the opposite occurs in magnitude-bit first mode. The clock relationships for serial
sign-bit first mode are illustrated in Figure 2-6.
In parallel master mode, the sign and magnitude receive data is output through
RQ[1] and RQ[0], respectively, on the rising edge of QCLK. The quaternary
transmit data is sampled on the falling edge of QCLK. This clock and data rela-
tionship is illustrated in Figure 2-7.
Figure 2-6. Serial Sign-Bit First Mode
QCLK
BCLK
RDAT
TDAT
Sign
0
Magnitude
0
Bit-Rate Clock
Sign
1
Magnitude
1
Sign
2
Sign
0
Magnitude
0
Sign
1
Magnitude
1
Sign
2
Figure 2-7. Parallel Master Mode
QCLK
Sign
0
Sign
2
Sign
1
Magnitude
0
Magnitude
1
Magnitude
2
RQ[1]/TQ[1]
RQ[0]/TQ[0]
