Registers
Register Summary
Bt8960
Single-Chip 2B1Q Transceiver
39
N8960DSB
0x0F reserved2 R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x10 sut1_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x11 sut1_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x12 sut2_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x13 sut2_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x14 sut3_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x15 sut3_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x16 sut4_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x17 sut4_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x18 meter_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x19 meter_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x20 reserved9 R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x1A snr_timer_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x1B snr_timer_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x1C t3_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x1D t3_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x1E t4_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x1F t4_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x21 adc_control R/W — — loop_back[1] loop_back[0] — gain[2] gain[1] gain[0]
0x22 pll_modes R/W clk_freq[1] clk_freq[0] —
phase_detector_
gain[1]
phase_detector_
gain[0]
freeze_pll pll_gain[1] pll_gain[0]
Table 3-1. Register Table (2 of 6)
ADDR
(hex)
Register
Label
Read
Write
Bit Number
7 6 5 4 3 2 1 0
