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4.0 Electrical & Mechanical Specifications
4.5 Channel Unit Interface Timing
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Table 4-11. Channel Unit Interface Timing Requirements, Serial Mode
Symbol Parameter Minimum Maximum Units
25 TDAT Setup prior to BCLK Falling Edge 100 ns
26 TDAT Hold after BCLK Low 25 ns
Table 4-12. Channel Unit Interface Switching Characteristics, Serial Mode
Symbol Parameter Minimum Maximum Units
27 BCLK Period T
QCLK
÷ 2 T
QCLK
÷ 2
28 BCLK Pulse-Width High T
QCLK
÷ 4 – 20 T
QCLK
÷ 4 + 20 ns
29 BCLK Pulse-Width Low T
QCLK
÷ 4 – 20 T
QCLK
÷ 4 + 20 ns
30 BCLK Hold after HCLK Rising Edge 0 ns
31 BCLK Delay after HCLK High 50 ns
32 RDAT, QCLK Hold after BCLK Rising Edge –50 ns
33 RDAT, QCLK Delay after BCLK High 50 ns
Figure 4-5. Channel Unit Interface Timing, Serial Mode
HCLK
BCLK
TDAT
QCLK
RDAT
25 26
27
28
29
30
31
32
33
