Registers
Register Summary
Bt8960
Single-Chip 2B1Q Transceiver
40
N8960DSB
0x23 reserved10 R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x24 pll_phase_offset_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x25 pll_phase_offset_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x26 dc_offset_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x27 dc_offset_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x28 tx_calibrate R/W — — tx_calibrate[3] tx_calibrate[2] tx_calibrate[1] tx_calibrate[0] — —
0x29 tx_gain R/W — — tx_gain[3] tx_gain[2] tx_gain[1] tx_gain[0] — —
0x2A noise_histogram_th_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x2B noise_histogram_th_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x2C ep_pause_th_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x2D ep_pause_th_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x2E scr_sync_th R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x30 far_end_high_alarm_th_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x31 far_end_high_alarm_th_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x32 far_end_low_alarm_th_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x33 far_end_low_alarm_th_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x34 snr_alarm_th_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x35 snr_alarm_th_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
0x36 cursor_level_low R/W D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0x37 cursor_level_high R/W D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
Table 3-1. Register Table (3 of 6)
ADDR
(hex)
Register
Label
Read
Write
Bit Number
7 6 5 4 3 2 1 0
