62
3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
not be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not exceeded,
the accumulator is cleared, the scrambler/descrambler re-enters the descrambler mode for
another 23 cycles, and the process repeats until either sync is achieved or this mode is dis-
abled. Once disabled, the sync interrupt flag can be cleared (if active) and the scram-
bler/descrambler returns to the mode specified by descr_on.
htur_lfsr Remote Unit (HTU-R/NTU) Polynomial Select—Read/write control bit that selects one of two
feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit
(HTU-R/NTU) receive polynomial (x
–23
+ x
–5
+ 1); when cleared, is selects the local unit
(HTU-C/LTU) polynomial (x
–23
+ x
–18
+ 1).
descr_on Descrambler/Scrambler Select—Read/write control bit that configures the scrambler/descram-
bler function as a descrambler when set, and as a scrambler when cleared. As a scrambler, this
bit can only generate a scrambled all ones sequence (constant high logic-level input); all
incoming data is ignored. In the auto scrambler synchronization mode (lfsr_lock = 1), this
selection is overwritten though the value of the control bit is unaffected.
3.2.42 0x3B—Peak Detector Delay Register (peak_detector_delay)
A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol
delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the
total path delay in each of the peak detector and slicer input paths according to the following formula: peak
detector delay register value = DAGC delays + FFE delays – fixed peak detector input delays. The DAGC and
FFE delays are not fixed, but result from the microprogrammed implementation of these functions. If used
unmodified, they equal 0 and 7, respectively. The fixed peak detector input delay is equal to 3.
3.2.43 0x3C—Digital AGC Modes Register (dagc_modes)
eq_error_
adaptation
Equalizer Error Adaptation—Read/write control bit that selects between the equalizer error
adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adapta-
tion uses the equalizer error signal produced by the slicer as the DAGC error input signal. In
self adaptation, the value of the DAGC Target Register [dagc_target_low, dagc_target_high;
0x38–0x39] is subtracted from the absolute value of the receive signal at the output of the
DAGC, and this difference is used as the error input signal.
adapt_coefficient Adapt Coefficients—Read/write control bit that enables coefficient adaptation when set; dis-
ables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is dis-
abled.
adapt_gain Adaptation Gain—Read/write control bit that specifies the adaptation gain. When set, the
adaptation gain is eight times higher than when cleared.
7 6 5 4 3 2 1 0
– – – – D[3] D[2] D[1] D[0]
7 6 5 4 3 2 1 0
– – – – –
eq_error_
adaptation
adapt_coefficient adapt_gain
