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Chapter 5 CPU Registers
2.Dedicated Registers
program.
■ ILM: Interrupt Level Mask Register
Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM)
• This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask.
• ILM indicates corresponding interrupt level from interrupt requests entered in CPU.
• Interrupt requests are accepted only if it’s priority is higher than the level.
• For level value, the highest priority is 0 (00000
B
), and the lowest priority is 31 (11111
B
).
• Program has some restrictions on configurable data.
• When original value is between 16 and 31,
Configurable new values are the value between 16 and 31.
If you execute the instruction to set the value between 0 and 15, “specified value +16” value is set.
• When original value is between 0 and 15,
You can set any value between 0 and 31.
These values are initialized to 15 (01111
B
) by reset.
20 19 18 17 16
[Initial value]
ILM4
01111
B
ILM3 ILM2 ILM1 ILM0
