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Chapter 6 EIT: Exceptions, Interrupts and Traps
5.EIT Interrupt Level
5. EIT Interrupt Level
Interrupt level is between 0 and 31, and controlled with 5 bits.
Only 16 through 31 levels are operable.
Undefined-instruction exception, coprocessor absent trap, coprocessor error trap and INT instruction are not
affected by interrupt level. Also, ILM is not changed by interrupt level.
6. EIT Vector Table
For EIT vector table, see the chapter of “3. Interrupt Vector Table (Page No.73)”.
Vector for EIT is between address which table-base register [TBR] indicates and a 1 kByte area.
Its size is 4 bytes per one vector. For vector number/vector address/trigger, see “3. Interrupt Vector Table
(Page No.73)”.
Address arithmetic is as follows.
Vector address = [TBR] + Offset value = [TBR] + {03FC
H
- 4 x Vector number (No.)}
Lower two bits as the result of addition are always used for “00”.
000FFC00
H
through 000FFFFF
H
areas are initial values of vector table by reset.
If you rewrite the TBR value, the mode and reset vectors always use the fixed address of 000FFFF8
H
,
000FFFFC
H
.
Table 5-1 Interrupt Level of EIT
Level
Description Remarks
Binary Decimal
00000
...
...
00011
00100
00101
...
...
01110
0
...
...
3
4
5
...
...
14
(Reserved for system)
...
...
(Reserved for system)
INTE instruction
Step trace trap
(Reserved for system)
...
...
(Reserved for system)
If original value of ILM is between 16 and 31, these
values are not configurable to ILM by program.
01111 15 NMI (for users)
10000
10001
...
...
11110
11111
16
17
...
...
30
31
Interrupt
Interrupt
...
...
Interrupt
N/A
When ILM is set, user Interrupt is disabled.
When ICR is set, Interrupt is disabled.
