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Chapter 33 I2C Controller
2.I2C Interface Registers
(Note) Because of the noise filter (depending on relationship between external signal and internal clock it
will cause different delays ) the divider in the second formula can vary between (12n + 19) and (12n
+ 20).
■ Prescaler settings:
Do not use n=0 prescaler setting, it violates SDA/SCL timings!
The table below shows SCL frequency measurement results for the most common R-bus clock settings and
the recommended related pre-scaler settings for 100 Kbit and 400 Kbit operation.
It should be noted that the measured values have been determined by examining the last 8 cycles of a
transfer. This was done because the first cycle of all address or data transfers is longer than the other cycles.
To be more precise: In case of an address transfer this first cycle is 3 prescaler periods longer than the other
cycles, in case of a data transfer it is 4 prescaler periods longer (see figure below).
Table 2-1 I2C Prescaler Settings
n CS4 CS3 CS2 CS1 CS0
100001
200010
300011
...
3111111
R-Bus Clock
(CLKP) [MHz]
100 kBit (Noise filter disabled)
n Bitrate [kBit]
400 kBit (Noise filter enabled)
n Bitrate [kBit]
32 5 387.5
24 19 97.5 4 352.5
16 12 98 2 372
8 6 89 1 266.5
Bitrate =
n*12 + 19 (+1)
φ
n>0; φ : R-Bus clock CLKP (set by DIVR0 register)
Noise filter enabled
(+1): Unaccurancy caused by noise filter operation
