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Chapter 29 MPU / EDSU
4.Registers
BIT[11]: UW - User default Write permission register
BIT[10]: UX - User default eXecute permission register
CPU and DMA Filter Option Register
BIT[9]: FCPU - Filter CPU access
FCPU controls the filter operation for CPU accesses triggered by operand compare channels (Operand address
break, data value break and memory data protection).
If FCPU is set to ’1’, all CPU acesses are masked out. If set to ’0’ CPU acesses can cause break function.
BIT[8]: FDMA - Filter DMA access
FDMA controls the filter operation for DMA accesses triggered by operand compare channels (Operand address
break, data value break and memory data protection).
If FDMA is set to ’1’, all DMA acesses are masked out. If set to ’0’ DMA acesses can cause break function.
Important Note for FDMA: Only DMA accesses over D-Bus were detected. The operands for an explicite DMA trig-
ger condition have to be located in the D-Bus address area (This is the case for D-bus RAM, CAN and all R-Bus
resources in the MB91460 family). Otherwise the DMA transfer could not be recognized by the EDSU. This function
was mainly intendet to disable the trigger on DMA accesses (filter out the operand change condition by DMA), com-
plete address range DMA trigger conditions are not supported.
Enable Interrupt Register
BIT[7]: EEMM - Enable Emulation Mode
0 User is not permitted to write data
1 User is permitted to write data (default)
0 User is not permitted to execute code
1 User is permitted to execute code (default)
0 Trigger on CPU accesses (default)
1 Do not trigger on CPU accesses
0 Trigger on DMA accesses (default)
1 Do not trigger on DMA accesses
0 Disable emulation mode (default)
