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■ Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR)
The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR,
ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial
interrupts, A/D conversion complete interrupts, and interrupt request/enable.
Be sure to disable all interrupts before writing to these registors.
Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR,
SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)
Chapter 2 Basic CPU Functions
35
Interrupts
xxxLV1
Interrupt level flag
xxxLV0
01245673
(at reset: 00----00)
TMnICR, TBICR, SCnICR,
ATCICR, ADICR
0
1
No interrupt request
Interrupt request flag
Happens interrupt request
xxxIE
xxxIR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
xxxIE
xxxIRxxxLV1xxxLV0 ––––
This 2-bit flag sets the interrupt level by
assigning an interrupt level of 0 to 3 to
interrupt requests.
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector will be disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.