Epson Research and Development Page 109
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Note that for EDO-DRAM and N
RP
= 1.5, this bit is automatically forced to 0 to select 2 MCLK for
N
RCD
. This is done to satisfy the CAS# address setup time, t
ASC
.
The resulting t
RC
is related to N
RCD
as follows:
t
RC
= (N
RCD
) T
M
if EDO and N
RP
= 1 or 2
t
RC
= (1.5) T
M
if EDO and N
RP
= 1.5
t
RC
= (N
RCD
+ 0.5) T
M
if FPM and N
RP
= 1 or 2
t
RC
= (N
RCD
) T
M
if FPM and N
RP
= 1.5
bits 3-2 RAS# Precharge Timing (N
RP
) Bits [1:0]
Minimum Memory Timing for RAS precharge
These bits select the DRAM RAS# Precharge timing parameter, t
RP
. These bits specify the number
(N
RP
) of MCLK periods (T
M
) used to create t
RP
- see the following formulae. Note, these formulae
assume an MCLK duty cycle of 50 +/- 5%.
N
RP
= 1 if (t
RP
/T
M
) < 1
= 1.5 if 1 ≤ (t
RP
/T
M
) < 1.45
= 2 if (t
RP
/T
M
) ≥ 1.45
The resulting t
RC
is related to N
RP
as follows:
t
RC
= (N
RP
+ 0.5) T
M
if FPM refresh cycle and N
RP
= 1 or 2
t
RC
= (N
RP
) T
M
for all other
Optimal DRAM Timing
The following table contains the optimally programmed values of N
RC
, N
RP
, and N
RCD
for different
DRAM types, at maximum MCLK frequencies.
bit 0 Reserved
Must be set to 0.
Table 8-12: RAS-to-CAS Delay Timing Select
REG[22h] Bit 4 N
RCD
RAS# to CAS# Delay (t
RCD
)
022 T
M
111 T
M
Table 8-13: RAS Precharge Timing Select
REG[22h] Bits [3:2] N
RP
RAS# Precharge Width (t
RP
)
00 2 2 T
M
01 1.5 1.5 T
M
10 1 1 T
M
11 Reserved Reserved
Table 8-14: Optimal N
RC
, N
RP
, and N
RCD
Values at Maximum MCLK Frequency
DRAM Type
DRAM Speed
(ns)
T
M
(ns)
N
RC
(#MCLK)
N
RP
(#MCLK)
N
RCD
(#MCLK)
EDO
50 25 4 1.5 2
60 30 4 1.5 2
70 33 5 2 2
FPM
60 40 4 1.5 2
70 50 3 1.5 1
