Page 54 Epson Research and Development
Vancouver Design Center
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
7.3.5 EDO-DRAM Self-Refresh Timing
Figure 7-11: EDO-DRAM Self-Refresh Timing
Table 7-11: EDO-DRAM Self-Refresh Timing
Symbol Parameter Min Typ Max Units
t1
Memory clock period
25 ns
t2
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 1.45 t1 ns
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 0.45 t1 ns
t3
CAS# precharge time (REG[22h] bits [3:2] = 00) 2 t1 ns
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 1 t1 ns
t4
CAS# setup time (REG[22h] bits [3:2] = 00 or 10)
0.45 t1 - 2 ns
CAS# setup time (REG[22h] bits [3:2] = 01)
1 t1 - 2 ns
t5
RAS# precharge time (REG[22h] bits [3:2] = 00) 2 t1 - 1 ns
RAS# precharge time (REG[22h] bits [3:2] = 01) 1.45 t1 - 1 ns
RAS# precharge time (REG[22h] bits [3:2] = 10) 1 t1 - 1 ns
RAS#
CAS#
t3
t2
t4
t5
Memory
Clock
Stopped for
suspend mode
Restarted for
active mode
t1
