Epson Research and Development Page 37
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
1. If the S1D13504 host interface is disabled, the timing for WAIT# driven is relative to the fall-
ing edge of CSn# or
the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
2. If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD# or
the first positive edge of CKIO after A[20:0] and M/R# become valid,
whichever occurs later.
Table 7-1: SH-3 Interface Timing
Symbol Parameter Min Max Units
t1
Clock period
25 ns
t2
Clock pulse width high
5ns
t3
Clock pulse width low
5ns
t4
A[20:0], M/R#, RD/WR# setup to CKIO
4ns
t5
A[20:0], M/R#, RD/WR# hold from CS#
0ns
t6
BS# setup
3ns
t7
BS# hold
0ns
t8
CSn# setup
0ns
t9
2
Falling edge RD# to D[15:0] driven
3ns
t10
Rising edge CSn# to WAIT# tri-state
04ns
t11
1
Falling edge CSn# to WAIT# driven
111ns
t12
CKIO to WAIT# delay
315ns
t13
D[15:0] setup to first CKIO after BS# (write cycle)
0ns
t14
D[15:0] hold (write cycle)
0ns
t15
D[15:0] valid to WAIT# rising edge (read cycle)
0ns
t16
Rising edge RD# to D[15:0] tri-state (read cycle)
29ns
