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Epson Research and Development Page 21
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor S1D13504
Issue Date: 01/02/02 X19A-G-010-05
Note
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
Note
It is important to note that when the MPC821 comes out of reset, its on-chip caches and
MMU are disabled. If the data cache is enabled, the MMU must be setup so the
S1D13504 memory block is tagged as non-cacheable. This ensures that accesses to the
S1D13504 will occur in proper order, and the MPC821 will not attempt to cache any
data read from or written to the S1D13504 or its display buffer.