Epson Research and Development Page 27
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
5.4.3 LCD Interface
1 Output may be 1 or 0.
5.4.4 Clock Input
Table 5-3: LCD
Interface Pin Descriptions
Pin Name Type
Pin #
Driver
Reset =
0 Value
Description
F00A
F!A
F02A
FPDAT[8:0] O 88, 82-75 98, 92-85 CN3 Output 0 Panel Data
FPDAT[15:9] O 95-89 105-99 CN3 Output 0
These pins have multiple functions.
• Panel Data for 16-bit panels.
• Pixel Data for external RAMDAC support.
See Table 5-11: “LCD, CRT, RAMDAC Interface Pin
Mapping,” on page 33.
FPFRAME O 69 79 CN3 Output 0 Frame Pulse
FPLINE O 70 80 CN3 Output 0 Line Pulse
FPSHIFT O 73 83 CN3 Output 0 Shift Clock Pulse
LCDPWRO 7181CO1Output
1
LCD power control output. The active polarity of this output
is selected by the state of MD10 at the rising edge of
RESET# - see Section 5.5,
“Summary of Configuration
Options”
on page 31.
This output is controlled by the power save mode circuitry -
see Section 13,
“Power Save Modes”
on page 128
for
details.
DRDY O 72 82 CN3 Output 0
This pin has multiple functions which are automatically
selected depending on panel type used.
• For TFT panels, this is the display enable output
(DRDY).
• For passive LCDs with Format 1 interfaces, this is the
2nd Shift Clock (FPSHIFT2).
• For all other LCD panels, this is the LCD backplane bias
signal (MOD).
See Table 5-11: “LCD, CRT, RAMDAC Interface Pin
Mapping,” on page 33
and REG[02h] for details.
Table 5-4: Clock Input
Pin Description
Pin Name Type
Pin #
Driver
Reset =
0 Value
Description
F00A
F01A
F02A
CLKI I 105 119 C Hi-Z
Input clock for the internal pixel clock (PCLK) and memory
clock (MCLK). PCLK and MCLK are derived from CLKI – see
REG[19h] for details.
