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S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
7.4.2 Suspend Timing
Figure 7-18: LCD Panel Suspend Timing
Note
1. t3, t5, and t7 are measured from the first CLKI after SUSPEND# inactive.
2. CLKI may be active throughout SUSPEND# active.
3. Where MCLK is the period of the memory clock.
Table 7-18: LCD Panel Suspend Timing
Symbol Parameter Min Typ Max Units
t1
LCDPWR inactive to CLKI inactive
128 Frames
t2
SUSPEND# active to FPFRAME, LCDPWR inactive
0 1 Frames
t3
First CLKI after SUSPEND# inactive to FPFRAME, LCDPWR
active
1Frames
t4
LCDPWR inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY
active
128 Frames
t5
First CLKI after SUSPEND# inactive to FPLINE, FPSHIFT,
FPDAT[15:0], DRDY active
0Frames
t6
LCDPWR inactive to Memory Access not allowed
8MCLK
t7
First CLKI after SUSPEND# inactive to Memory Access allowed
0MCLK
FPLINE
DRDY
SUSPEND#
t1
t5
t2
t4
t3
CLKI
LCDPWR
FPSHIFT
FPDAT[15:0]
Active
Inactive
Active
Active
Active
Active
Active
Inactive
Allowed
Allowed
Not Allowed
Memory Access
t6
Software Suspend
FPFRAME
t7
Note 1
Note 2
