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Page 12 Epson Research and Development
Vancouver Design Center
S1D13504 13504DCFG Configuration Program
X19A-B-008-02 Issue Date: 01/02/01
The Clocks Tab allows the user to select the following settings.
Note
For further information on clocks, see the S1D13504 Hardware Functional Specifica-
tion, document number X19A-A-002-xx.
Clocks Tab
CLKI Selects the frequency of CLKI in kHz.
LCD Auto
Determines the optimal value for CLKI for the LCD. LCD Auto
and CRT Auto cannot be selected at the same time.
CRT Auto
Determines the optimal value for CLKI for the CRT. LCD Auto
and CRT Auto cannot be selected at the same time.
LCD MCLK:PCLK
Selects the divide ratio used to generate the pixel clock (PCLK)
from the memory clock (MCLK) for the LCD. Checking auto
automatically sets the divide ratio for the LCD PCLK.
CRT MCLK:PCLK
Selects the divide ratio used to generate the pixel clock (PCLK)
from the memory clock (MCLK) for the CRT. Checking auto
automatically sets the divide ratio for the CRT PCLK.
BUSCLK Selects the frequency of BUSCLK in kHz.
MCLK Divide
Selects the divide ratio used to generate the internal memory
clock (MCLK) from CLKI.