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Page 46 Epson Research and Development
Vancouver Design Center
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
7.2 Clock Input Requirements
Figure 7-6: Clock Input Requirements
Note
When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).
There is no minimum frequency for CLKI.
Table 7-6: Clock Input Requirements
Symbol Parameter Min Typ Max Units
T
CLKI
Input Clock Period (CLKI) 12.5 ns
T
PCLK
Pixel Clock Period (PCLK) not shown 25 ns
T
MCLK
Memory Clock Period (MCLK) not shown 25 ns
t
PWH
Input Clock Pulse Width High (CLKI) 45% 55% T
CLKI
t
PWL
Input Clock Pulse Width Low (CLKI) 45% 55% T
CLKI
t
PWL
t
PWH
Clock Input Waveform
T
CLKI
V
IH
V
IL