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Chapter 3 Interrupts
III - 12
Overview
■Multiplex Interrupt
When an MN101C77 series device accepts an interrupt, it automatically disables acceptance of subse-
quent interrupts with the same or lower priority level. When the hardware accepts an interrupt, it copies the
interrupt level (xxxLVn) for the interrupt to the interrupt mask (IM) in the PSW. As a result, subsequent
interrupts with the same or lower priority levels are automatically masked. Only interrupts with higher
priority levels are accepted. The net result is that interrupts are normally processed in decreasing order of
priority. It is, however, possible to alter this arrangement.
1. To disable interrupt nesting
- Reset the MIE bit in the PSW to "0."
- Raise the priority level of the interrupt mask (IM) in the PSW.
2. To enable interrupts with lower priority than the currently accepted interrupt
- Lower the priority level of the interrupt mask (IM) in the PSW.
Multiplex interrupts are only enabled for interrupts with levels higher than the PSW interrupt
mask level (IM).
Do not operate the maskable interrupt control register (xxxICR) when multiple interrupts are
enabled. If operation is necessary, first clear the PSW MIE flag to disable interrupts.
It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt
being processed, but be careful of stack overflow.