Filter
Top Products
Chapter 3 Interrupts
III - 22
Control Registers
■Timer 0 Interrupt Control Register (TM0ICR)
The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
Figure 3-2-8 Timer 0 Interrupt Control Register (TM0ICR : x'03FE9', R/W)
TM0
LV1
Interrupt level flag
TM0
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
TM0IE
TM0IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
TM0IE
TM0IR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
TM0
LV0
TM0
LV1
TM0ICR