Filter
Top Products
Chapter 3 Interrupts
III - 18
Control Registers
■External Interrupt 1 Control Register (IRQ1ICR)
The external interrupt 1 control register (IRQ1ICR) controls interrupt level of external interrupt 1, active
edge, interrupt enable and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-3 External Interrupt 1 Control Register (IRQ1ICR : x'03FE3', R/W)
IRQ1
LV1
Interrupt level flag
for external interrupt
IRQ1
LV0
01245673
(At reset : 0 0 0 - - - 0 0 )
IRQ1ICR
0
1
No interrupt request
External interrupt request flag
Interrupt request generated
IRQ1IE
IRQ1IR
0
1
Disable interrupt
External interrupt enable flag
Enable interrupt
IRQ1IE
0
1 Rising edge
External interrupt active edge flag
Falling edge
The CpU has interrupt levels from 0 to 3. These
flag set the interrupt level for interrupt requests.
REDG1
IRQ1IR
IRQ1
-
LV1
IRQ1
LV0
REDG1
-
-