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Chapter 2 CPU Basics
II - 8
Overview
2-1-7 Processor Status Word
Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask
level, and maskable interrupt enable. PSW is automatically pushed onto the stack when an interrupt
occurs and is automatically popped when return from the interrupt service routine.
Figure 2-1-3 Processor Status Word(PSW)
76543210
NF ZF
ZF
Operation result is not "0".0
1
Zero flag
Operation result is "0".
NF
0
1
Negative flag
MSB of operation results is "1".
MSB of operation results is "0".
VF
Overflow did not occur.0
1
Overflow flag
Overflow occured.
IM1 to 0
Controls maskable interrupt acceptance.
Interrupt mask level
PSW
( At reset : 0 0 0 0 0 0 0 0 )
CF
A carry or a borrow from MSB
did not occur.
0
1
Carry flag
A carry or a borrow from MSB
occured.
MIE
All maskable interrupts are
disabled.
0
1
Maskable interrupt enable
(xxxLVn,xxxIE) for each interrupt
are enabled.
Reserved
Set always "0".
CFVFIM0IM1MIE
Reserved