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Chapter 3 Interrupts
III - 32
Control Registers
■Serial Interface 1 Reception Interrupt Control Register (SC1ICR)
The serial Interface 1 reception interrupt control register (SC1ICR) controls interrupt level of serial
Interface 1 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register
should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-20 Serial Interface 1 Reception Interrupt Control Register (SC1ICR : x'03FF6', R/W)
SC1R
LV1
Serial interface 1 reception
interrupt level flag
SC1R
LV0
01245673
(at reset : 0 0 - - - - 0 0 )
0
1
No interrupt request flag
Serial interface 1 reception
interrupt request flag
Interrupt request generated
SC1RIE
SC1RIR
0
1
Disable interrupt
Serial interface 1 reception
interrupt enable flag
Enable interrupt
SC1RIE
SC1RIR
----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
SC1R
LV0
SC1R
LV1
SC1RICR