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Chapter 3 Interrupts
Control Registers
Figure 3-2-2 External Interrupt 0 Control Register (IRQ0ICR : x'03FE2', R/W)
IRQ0
LV1
Interrupt level flag
for external interrupt
IRQ0
LV0
01245673
(At reset : 0 0 0 - - - 0 0)
IRQ0ICR
0
1
No interrupt request
External interrupt
request flag
Interrupt request generated
IRQ0IE
IRQ0IR
0
1
Disable interrupt
External interrupt
enable flag
Enable interrupt
IRQ0IE
0
1 Rising edge
External interrupt active
edge flag
Falling edge
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for interrupt
request.
REDG0
IRQ0IR
IRQ0
---
LV1
IRQ0
LV0
REDG0
■External Interrupt 0 Control Register (IRQ0ICR)
The external interrupt 0 control register (IRQ0ICR) controls interrupt level of the external interrupt 0,
active edge, interrupt enable and interrupt request. Interrupt control register should be operated when
the maskable interrupt enable flag (MIE) of PSW is "0".