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Chapter 3 Interrupts
Control Registers
■Timer 5 Interrupt Control Register (TM5ICR)
The timer 5 interrupt control register (TM5ICR) controls interrupt level of timer 5 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
Figure 3-2-13 Timer 5 Interrupt Control Register (TM5ICR : x'03FEE', R/W)
TM5
LV1
Interrupt level flag
TM5
LV0
01245573
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
TM5IE
TM5IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
TM5IE
TM5IR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
TM5
LV0
TM5
LV1
TM5ICR