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Chapter 3 Interrupts
III - 36
Control Registers
■A/D Converter Interrupt Control Register (ADICR)
The A/D converter interrupt control register (ADICR) controls interrupt level of A/D converter interrupt,
interrupt enable flag and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-25 A/D Converter Interrupt Control Register (ADICR : x'03FFA', R/W)
AD
LV1
Interrupt level flag
AD
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
ADIE
ADIR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
ADIE
ADIR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
AD
LV0
AD
LV1
ADICR