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Chapter 3 Interrupts
Control Registers
■Serial Interface 4 Interrupt Control Register (SC4ICR)
The serial interface 4 interrupt control register (SC4ICR) controls interrupt level of serial interface 4
interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when
the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-24 Serial Interface 4 Interrupt Control Register (SC4ICR : x'03FF3', R/W)
SC4
LV1
Interrupt level flag
SC4
LV0
01245674
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
SC4IE
SC4IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
SC4IE
SC4IR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
SC4
LV0
SC4
LV1
SC4ICR