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Chapter 3 Interrupts
III - 34
Control Registers
■Serial Interface 3 Interrupt Control Register (SC3ICR)
The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3
interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when
the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-23 Serial Interface 3 Interrupt Control Register (SC3ICR : x'03FF9', R/W)
SC3
LV1
Interrupt level flag
SC3
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
SC3IE
SC3IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
SC3IE
SC3IR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
SC3
LV0
SC3
LV1
SC3ICR