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Connectors
Signal Descriptions for SYSTEM BUS
RP_HOP_ADRS0,
through
RP_HOP_ADRS9,
RP_HOP_ADRS10
ADRS0-Pin 12, ADRS1-Pin 31 ADRS2-Pin 13, ADRS3-Pin 32 ADRS4-Pin 14,
ADRS5-Pin 33 ADRS6-Pin 15, ADRS7-Pin 34 ADRS8-Pin 16, ADRS9-Pin 35
ADRS10-Pin 17, Inputs
These are the rear-panel hop frequency table address input lines. They connect to the
to hop controller. These lines select entries from user-entered RF generator and RF
analyzer hop frequency tables. These lines have multiple uses, depending on the
selected modes.
1 Used in combination with RP_TX_HOP to frequency hop the RF generator.
2 Used in combination with RP_RX_HOP to frequency hop the RF analyzer.
3 Used in combination with RP_RST_SEQ_HOP to reset the internal hop address
register.
These signals are read on the positive-going edge of RP_TX_HOP when the RF
generator’s hop mode is set to Hop, the hop trigger is set to Arm, and the hop
address source is set to Ext.
These signals can also be read on the positive-going edge of RP_RX_HOP when the
RF analyzer’s hop mode is set to Hop, the hop trigger is set to Arm, and the hop
address source is set to Ext.
Or, these signals are read on the positive going edge on RP_SEQ_HOP when the
address source is set to Seq, the RF analyzer’s hop trigger is set to Arm, or RF
generator’s hop trigger is set to Arm.
Requirements Amplitude: TTL levels High drive requirement: 100 µA Low
drive requirement: 1 mA Format: unassigned binary, high=1.
See Also Screens: RFG/RFA (Hop Control) Specifications Timing
Diagrams