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Chapter 3 Interrupts
Overview
MIE='0' and interrupts are disabled when:
- MIE in the PSW is reset to '0' by a program
- Reset is detected
MIE='1' and interrupts are enabled when:
- MIE in the PSW is set to '1' by a program
The interrupt mask level (IM=IM1 - IM0) in the processor status word (PSW) changes when:
- The program alters it directly,
- A reset initializes it to 0 (00b),
- The hardware accepts and thus switches to the interrupt level (IL) for a maskable interrupt, or
- Execution of the RTI instruction at the end of an interrupt service routine restores the processor
status word (PSW) and thus the previous interrupt mask level.
The maskable interrupt enable (MIE) flag in the processor status word (PSW) is not
cleared to "0".
Non-maskable interrupts have priority over maskable ones.