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Chapter 17 Appendices
Instruction Set
MN101C SERIES INSTRUCTION SET
Group Mnemonic Operation
Flag
VF
NF CF ZF
Code
Size
Cycle
Re-
peat
Machine Code
Notes
1
234567891011
Exten-
sion
Contorl instructions
REP imm3
REP *1imm3-1→RPC
--- --- --- ---
32
0001
1rep0010
*1 no repeat whn imm3=0, (rep: imm3-1)
RTS
RTS mem8(SP)→(PC).bp7-0
--- --- --- ---
27
0000
0001
mem8(SP+1)
→
(PC).bp15-8
mem8(SP+2).bp7
→
(PC).H
mem8(SP+2).bp1-0
→
(PC).bp17-16
SP+3→SP
RTIRTI mem8(SP)→PSW
211
0000
0011
mem8(SP+1)→(PC).bp7-0
mem8(SP+2)
→
(PC).bp15-8
mem8(SP+3).bp7
→
(PC).H
mem8(SP+3).bp1-0
→
(PC).bp17-16
mem8(SP+4)→HA-l
mem8(SP+5)→HA-h
SP+6→SP
Ver3.2(2002.01.31)
macro instructions
replaced instructions
remarks
Other than the instruction of MN101C Series,the assembler of this Series has the following instructions
as macro instructions.
The assembler will interpret the macro instructions below as the assembler instructions.
INC
DEC
INC
DEC
INC2
DEC2
CLR
ASL
ROL
NEG
NOPL
MOV
MOV
MOVW
MOVW
MOVW
MOVW
ADD
ADD
ADDW
ADDW
ADDW
ADDW
SUB
ADD
ADDC
NOT
ADD
MOVW
MOV
MOV
MOVW
MOVW
MOVW
MOVW
n=m
n=m
n=m
n=m
Dn
Dn
Dn
Dn
Dn
Dn
An
An
An
An
(SP),Dn
Dn,(SP)
(SP),DWn
DWn,(SP)
(SP),An
An,(SP)
1,Dn
-1,Dn
1,An
-1,An
2,An
-2,An
Dn,Dm
Dn,Dm
Dn,Dm
Dn
1,Dn
DWn,DWm
(0,SP),Dn
Dn,(0,SP)
(0,SP),DWn
DWn,(0,SP)
(0,SP),An
An,(0,SP)
LSL
ADD
n=m
Dn
Dn,Dm