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Chapter 11 Serial Interface 0, 1
XI - 30
Operation
Reception Timing
Figure 11-3-9 Reception Timing (rising edge, start condition is enabled)
Figure 11-3-10 Reception Timing (rising edge, start condition is disabled)
T
Clock
(SBT pin)
Input data
(SBI pin)
SCnRBSY
Interrupt
(SCnTIRQ)
Transfer bit counter
01234567
∆
(Write data to TXBUFn)
(at master)
Tmax=2.5 T
T
Clock
(SBT pin)
Input data
(SBI pin)
SCnRBSY
Interrupt
(SCnTIRQ)
Transfer bit counter
01234567
∆
(Write data to TXBUFn)
(at master)
Tmax=1.5 T