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Chapter 3 Interrupts
Control Registers
■Time Base Interrupt Control Register (TBICR)
The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
Figure 3-2-15 Time Base Interrupt Control Register (TBICR : x'03FF0', R/W)
TB
LV1
Interrupt level flag
TB
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
TBIE
TBIR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
TBIE
TBIR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
TB
LV0
TB
LV1
TBICR