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Chapter 3 Interrupts
Control Registers
■External Interrupt 2 Control Register (IRQ2ICR)
The external interrupt 2 control register (IRQ2ICR) controls interrupt level of external interrupt 2, active
edge, interrupt enable and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-4 External Interrupt 2 Control Register (IRQ2ICR : x'03FE4', R/W)
IRQ2
LV1
Interrupt level flag for external interrupt
IRQ2
LV0
01245673
(At reset : 0 0 0 - - - 0 0)
IRQ2ICR
0
1
No interrupt request
External interrupt request flag
Interrupt request generated
IRQ2IE
IRQ2IR
0
1
Disable interrupt
External interrupt enable flag
Enable interrupt
IRQ2IE
0
1 Rising edge
External interrupt active edge flag
Falling edge
The CPU has interrupt levels from 0 to 3. These
flags set the interrupt level for interrupt requests.
REDG2
IRQ2IR
IRQ2
---
LV1
IRQ2
LV0
REDG2